Job Description

President at SBT | 19 years of advising leaders at semiconductor and deep tech companies | Architecting teams from startups to F500 organizations

Company Overview

This confidential client is strategically bringing on a Director of Physical Design Engineering to build and lead a PD organization from the ground up. This is a highly technical, handson leadership role responsible for architecting physical implementation strategy, driving execution across complex SoCs, and shaping the longterm direction of the companys chip development efforts. The Director will collaborate crossfunctionally with systems hardware teams, software architects, and executive leadership while guiding a growing team through the full lifecycle of advanced semiconductor development.

Responsibilities

• Provide handson technical leadership across complex physical design activities, including clock/reset architecture, power delivery networks, floorplanning, routing strategies, and interconnect topology development.
• Drive endtoend physical implementationfrom synthesis, floorplanning, power planning, and placeandroute through timing closure, physical verification, and final tapeout.
• Build and scale a Physical Design organization from scratch, including hiring, mentoring, establishing methodologies, and defining bestinclass PD workflows.
• Partner with architects and microarchitects to define, explore, and construct major physical structures at block, cluster, and top levels.
• Collaborate closely with crossfunctional teams to ensure seamless product execution and successful highvolume silicon readiness.

Qualifications

• 10+ years of industry experience in Physical Design engineering, with deep expertise across fullchip implementation, advanced nodes, multiIP integration, timing closure, and tapeout signoff.
• 5+ years of leadership experience, including building and leading Physical Design teams or organizations.
• Demonstrated success owning toplevel floorplanning, clock/power distribution, physical verification, and largescale P&R implementation.
• Strong experience collaborating with architecture, RTL design, packaging, and system teams on complex SoC programs.
• Experience with DSPbased chip architectures is a strong preference.

This role is remote with occasional travel to the onsite location.

Seniority level

Director

Employment type

Fulltime

Job function

Semiconductor Manufacturing and Computer Hardware Manufacturing

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